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Description: PCI总线仲裁参考设计,Quicklogic提供的verilog代码-PCI bus arbitration reference design, pioneered the Verilog code
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Size: 3480 |
Author: 陈旭 |
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Description: pci接口的verilog原代码,定义了pci接口所需要的全部引脚
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Size: 4260 |
Author: david |
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Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented
PCI Bus interface. This interface is available in 32-bit and 64-
bit versions, with support for multiple Xilinx FPGA device families. It
is designed to support both Verilog-HDL and VHDL. The design
examples in this book are provided in Verilog.
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Size: 899078 |
Author: lee |
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Description: pci设计verilog,可参考
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Size: 108449 |
Author: guolh_bj |
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Description: FPGA_ASIC设计资料 代码集合-FPGA_ASIC design information source pool
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Size: 4000768 |
Author: 李强 |
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Description: USB接口的VHDL源码,支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
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Size: 230400 |
Author: 王森 |
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Description: 这个我也太清楚是什么 反正师兄们说有用 发大家-I am also very clear that what is useful anyway, say senior U.S. fa
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Size: 430080 |
Author: wang |
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Description: PCI Express Specification
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Size: 550912 |
Author: khj |
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Description: PCI express CRC rtl core for Fpga/asic Designer
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Size: 202752 |
Author: 李晓媛 |
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Description: uart pci 等verilog hdl 代码-uart pci such as verilog hdl code
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Size: 7168 |
Author: skdk |
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Description: 华为,大规模逻辑设计指导书,规格详细,包括:VHDL编写规范,Verilog编写规范,asic设计方法,同步电路设计规则,vhdl电路设计,代码可重用设计,-Huawei, a large-scale logic design guide books, detailed specifications, including: VHDL specification preparation, Verilog specification preparation, asic design, synchronous circuit design rules, vhdl circuit design, reusable code design,
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Size: 2041856 |
Author: feng jee |
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Description: fpga开发pci的verilog,不可多得的源代码。-FPGA development pci of verilog, rare source code.
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Size: 1726464 |
Author: 王军 |
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Description: verilog开发的PCI target模块,能完成配置空间的读写以及单次的memory读写,原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
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Size: 10240 |
Author: 齐培红 |
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Description: PCI arbi verilog source code
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Size: 3072 |
Author: bulbul1225 |
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Description: verilog编写的PCI总线,提供了Wishbone bus和PCI local bus之间的接口,内由两个独立的模块组成,分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus
and the PCI local bus. It consists of two independent units, one handling transactions
originating on the PCI bus, the other one handling transactions originating on the
WISHBONE bus.
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Size: 13253632 |
Author: yemao |
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Description: 一个基于FPGA的PCI数据发送程序,实现从计算机通过PCI9054向FPGA发送数据功能。开发语言verilog,开发环境quartus-FPGA-based PCI data distribution process, from the computer through the PCI9054 functions to send data to the FPGA. The development of language verilog, development environment quartusII
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Size: 236544 |
Author: 李国扬 |
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Description: pci target design verilog file
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Size: 53248 |
Author: peter |
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Description: PCI Verilog source code
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Size: 167936 |
Author: jc |
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Description: PCI 32bit Slave Verilog 代码-PCI 32bit Slave Verilog code
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Size: 18432 |
Author: chen |
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Description: 基于PCI的DIO接口程序,包括verilog源程序、驱动源程序以及寄存器说明文件-PCI-DIO-based interface program, including the verilog source code, driver source code and documentation register
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Size: 2309120 |
Author: zifeng |
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